Shrike RP2040 and FPGA Targets

Build

firmware/shrike/rp2040/Cargo.toml now declares an empty [workspace], so the firmware builds standalone even when the checkout is a nested worktree. Build from the firmware directory so the target linker configuration applies (the bench record excludes an earlier root-directory build that omitted it):

firmware/shrike/rp2040/build-uf2.sh

The script builds the release ELF, converts it with a pinned elf2uf2-rs 2.2.0, runs verify_flash_contract.py, and writes a .sha256 sidecar.

Run host tests

cargo test -p shrike_control
cargo test -p shrike_rp2040_host_sim
python3 firmware/shrike/rp2040/host-tests/test_flash_contract.py

The simulation crate gains paired_control.rs and fpga_lifecycle.rs on this branch; see Drivers and Control Link.

Recovery before custom flashing

flash-uf2.sh verifies the hash sidecar and the flash contract before copying. The contract requires a ready factory recovery image. On this branch SOURCE.toml records factory_uf2.ready = true for the vendor shrike-lite-micropython-v1.0.0.uf2 (SHA-256 fe776218...b42648), which is now checked in.

The observed entry procedure is: with USB connected, hold BOOT, press and release RST, then release BOOT. The RP2040 ROM enumerates as 2e8a:0003 (RPI-RP2). Cold BOOT-held USB reconnection failed three times on the identified board; the cause is unknown.

Simulate

scripts/verify/fpga-safety-gate.sh

This runs the tb_shrike_safety_gate testbench and the tb_axiomos_r04_top runtime-link testbench with iverilog. It produces no synthesis or bitstream evidence.

Yosys preflight

From the repository root, with the Renesas-bundled Yosys:

yosys -s scripts/verify/fpga-safety-preflight.ys
yosys -s scripts/verify/fpga-mapping-preflight.ys

The second check rejects mapped latches and checks carry blocks against the 140-CLB tile. Neither qualifies pins or produces a bitstream.

Synthesize in Forge

Open firmware/shrike/fpga/forgefpga/axiomos_r04.ffpga. It registers clk_50mhz.sdc. For the robustness build, replace it with clk_18ns_guard.sdc; never load both. Keep the checked-in mapping and packing settings; changing them requires fresh simulation and timing evidence.

Verify retained build evidence

python3 -B scripts/verify/fpga-build-evidence.py --evidence-dir \
  .superpowers/sdd/shrike-fpga-bench/vendor-synthesis/timing-closure-20260912

The evidence directory is ignored, operator-local material. The verifier checks the manifest and six builds against the current RTL, settings, SDC and pins, and never rewrites evidence. Its tests run with python3 -B tests/scripts/test_fpga_build_evidence.py.